Build the evidence, then build the machine.
The roadmap advances through technical evidence and acceptance gates rather than public calendar promises.
Sequence is directional and changes with engineering evidence
- 01activeWorkload contracts and RISC-V reference platforms
- 02activeProtonSim and architecture performance modeling
- 03plannedProton SDK, runtime, and llama.cpp backend
- 04plannedProton LPU-E0 RTL and verification
- 05futureFPGA reference system
- 06futureOpen ASIC exploration
- 07futureProton LPU-E1 multi-tile edge architecture
- 08long-termProton LPU-S1 server research
A stage advances when its outputs support the next decision.
Workload contracts, validated models, software artifacts, RTL verification, implementation results, and review decisions form the gates between stages.
Workload contracts, simulation, and reference enablement come first.
Proton NPU has reached a published bare-metal RTL milestone. The next work builds on that reference while the Proton LPU architecture, FPGA, ASIC and multi-tile directions retain their separate research and roadmap status.
E1 and S1 remain roadmap families, not announced products.
Proton LPU-E1 represents a future scalable edge direction. Proton LPU-S1 represents longer-term server-class research.
Evidence may reorder, split, or retire a stage.
A stage-based roadmap preserves technical honesty while the architecture, software, and evidence mature.