CEREBRALCHIPSFollow the build
EDGE AI HARDWARE + SOFTWARE

Every machine should think.

Cerebral Chips is building the hardware, software, simulators, and AI-native engineering systems required to run language models directly inside devices—private, efficient, and independent of permanent cloud connectivity.

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CC / 001
Architecture and prototype phase
SYSTEM / PROTONLOCAL
INPUT / TOKEN STREAMSTATE / RESEARCH
Intelligence contained inside a compute deviceA five-node neural mesh receives a token signal and resolves it locally inside an octagonal device frame.
The Neural Mesh represents intelligence connected and contained inside the device.
SCROLL / 01
01

THE MISSION

Move intelligence from the cloud into the machine.

Language models are becoming part of products, robots, industrial systems, vehicles, personal devices, and embedded interfaces. Those systems need local intelligence with predictable latency, privacy, and operation even when the cloud is unavailable.

Cerebral Chips is building that foundation from workload analysis and software integration down to the instruction architecture, memory system, and quantized datapath.

01
WORKLOAD EVIDENCEModel workload

Observe operators, shapes, movement, and quantization.

02
ARCHITECTURE DECISIONSMeasured architecture

Turn measured behavior into explicit compute tradeoffs.

03
DEVICE EXECUTIONDevice execution

Keep intelligence responsive, private, and local.

02

HARDWARE × SOFTWARE CO-DESIGN

Modern edge AI needs one system, not two disconnected roadmaps.

Cerebral Chips treats models, quantization, compilers, runtimes, firmware, instruction architecture, matrix and vector execution, and memory movement as one connected design problem. Real workload behavior drives the machine; hardware constraints reshape the software path.

SOFTWARE SYSTEMMake the workload programmable
S1Models and quantization
S2Compiler and runtime
S3Kernels and profiling
ACTIVE CO-DESIGN LOOP

Start with what the model actually does.

Prefill, decode, operator mix, tensor shapes, and quantization behavior establish the first design contract.

HARDWARE SYSTEMMake the workload efficient
H1ISA and command model
H2Vector and matrix engines
H3Scratchpad, DMA, and memory
ONE WORKLOAD CONTRACT
CORRECTNESSLOCALITYBANDWIDTHLATENCYEFFICIENCY
ONE EVIDENCE LOOP
03

THE PROTON PLATFORM

A complete stack for on-device language intelligence.

The Proton platform connects model workloads, developer software, architecture simulation, agentic engineering, and accelerator hardware. Each layer exists to make the next layer measurable, programmable, and verifiable.

P-01Research
LPU

Proton LPU

A quantization-native, memory-aware language-processing accelerator architecture.

PRIMARY AUDIENCEHardware engineers / AI inference engineers

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P-02In development
SDK

Proton SDK

A planned developer path from GGUF models and llama.cpp to runtime, kernels, and profiling.

PRIMARY AUDIENCECompiler engineers / Runtime engineers

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P-03Prototype
Sim

ProtonSim

A workload and architecture simulator for choosing hardware from measurable model behavior.

PRIMARY AUDIENCEPerformance engineers / Hardware architects

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P-04Prototype
Forge

Proton Forge

An evidence-gated engineering system for accelerating hardware and software iteration.

PRIMARY AUDIENCEHardware engineers / Software engineers

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04

PROTON LPU / PROPOSED ARCHITECTURE

Language-model hardware designed around real inference behavior.

Proton LPU is a proposed RISC-V-controlled accelerator architecture for quantized transformer inference. It combines vector execution, quantization-aware matrix compute, explicitly managed local memory, DMA, external-memory access, device firmware, and a practical llama.cpp software path.

SYSTEM MAP / EDITABLECandidate execution architecture
Research
01Host systemModel orchestration and command submission
02RISC-V controlFirmware, queues, and execution control
03Vector engineElementwise, reduction, and support operations
04Quantized matrix engineGEMM and GEMV execution candidates
05Local scratchpadExplicitly managed working data
06DMA + external memoryScheduled data movement and model storage

Logical architecture view. Interfaces and parameters remain subject to workload-driven evaluation.

MATRIX ENGINE / MAPPING VIEW8 × 8 outer-product candidate
Under evaluation
PARTIAL SUMS / INT32 DIRECTION
01Parallel products

Eight activation lanes interact with eight weight lanes.

02Dataflow study

GEMM, GEMV, and reduction behavior remain under evaluation.

03Complete quantization path

Scale, zero-point, accumulation, and output handling stay in scope.

Primary workloadProposed
Dense decoder-only transformer inference

The first workload contract is intentionally narrow and measurable.

Initial model envelopeUnder evaluation
Approximately 0.5B–1.5B parameters

A 3B parameter model remains a stretch target.

Arithmetic directionProposed
Four-bit weights, eight-bit activations, INT32 accumulation

Exact GGUF quantization coverage will be selected through bring-up work.

Matrix candidateUnder evaluation
8 × 8 physical MAC fabric

GEMM and GEMV dataflows are evaluated independently.

Compute scratchpadUnder evaluation
128 KB, 256 KB, and 512 KB study

256 KB is a working baseline, not a finalized choice.

05

PROTON SDK / SOFTWARE PATH

From downloadable model to device execution.

The initial software path starts with GGUF models and llama.cpp. A Proton GGML backend, userspace runtime, firmware, kernels, command queues, and profiling tools connect model execution to the accelerator. IREE remains a future frontend and compiler integration path.

INITIAL EXECUTION PATHIn development
  1. 01GGUF modelMODEL
  2. 02llama.cpp / GGMLHOST SOFTWARE
  3. 03Proton backendHOST SOFTWARE
  4. 04Proton runtimeHOST SOFTWARE
  5. 05Firmware and kernelsDEVICE PATH
  6. 06Proton LPU or ProtonSimDEVICE PATH
FUTURE FRONTEND PATH
IREEFuture
06

PROTONSIM / DESIGN SPACE

Design the hardware from workload evidence.

ProtonSim models the work, memory movement, and execution behavior of real transformer workloads before architecture choices are frozen. It is intended to connect model operators and quantization formats to decisions such as vector width, matrix shape, scratchpad capacity, DMA behavior, and external-memory bandwidth.

EXAMPLE STUDY INPUTSArchitecture explorer
Prototype
Workload phase
Quantization format
Matrix shape
NO RESULT GENERATEDConnect a validated workload model to view results.

Controls illustrate the intended design space. They do not represent benchmark results or finalized specifications.

Selected workload
Decode
Quantization study
Grouped INT4
Compute candidate
8 × 8
07

AI-NATIVE ENGINEERING

Agents accelerate the work. Evidence decides what ships.

Proton Forge is an agentic engineering system for specification analysis, architecture exploration, RTL and verification scaffolding, firmware, kernel generation, documentation, and regression triage.

Generated artifacts are never accepted on model confidence alone. They pass through deterministic builds, reference-model comparison, randomized tests, assertions, coverage, synthesis, and human review.

EVIDENCE-GATED PIPELINEPrototype
01Requirements
02Structured specification
03Workload model
04Design or code generation
05Compile and lint
06Golden-reference comparison
07Randomized testing
08Coverage and synthesis regression
09Human review
ACCEPT ONLY WITH REPRODUCIBLE EVIDENCE
08

KERNEL GENERATION / VERIFY

Target-specific kernels with reproducible verification.

The Proton toolchain is being designed to generate and tune custom kernels for vector and matrix targets from structured specifications. The accepted result is a versioned artifact backed by compilation, numerical differential testing, edge-case coverage, and performance evidence.

kernel.spec / illustrativeREAD ONLY
target: proton_vector_matrix
operation: quantized_linear
weights: grouped_int4
activations: int8_candidate
accumulation: int32
accept_if:
  - compiles
  - matches_reference
  - passes_edge_cases
01Compile
02Numerical diff
03Edge cases
04Versioned evidence
09

PROTON SDK / REFERENCE ENABLEMENT

Build useful systems before custom silicon is complete.

The Proton SDK will include reference-platform enablement that reuses suitable open-source RISC-V cores, toolchains, runtimes, and ML projects to validate model execution and hardware–software integration early. These environments create testable engineering artifacts while the custom LPU architecture matures.

Reference repositories and verified bring-up notes will be published as they are ready.

OPEN ENGINEERING

Open from assumptions to implementation.

Cerebral Chips intends to publish architecture notes, workload models, quantization references, RTL, software, verification methods, FPGA work, benchmark methodology, and design-decision records where technically and legally practical.

01Architecture notes
02Workload models
03Quantization references
04RTL and verification
05Software and firmware
06FPGA bring-up
07Benchmark methodology
08Decision records
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10

ROADMAP / STAGE-BASED

Build the evidence, then build the machine.

The roadmap follows technical evidence rather than calendar promises. Each stage reduces uncertainty for the architecture, software path, and reference system that follows.

  1. 01
    Active

    Workload contracts and RISC-V reference platforms

  2. 02
    Active

    ProtonSim and architecture performance modeling

  3. 03
    Planned

    Proton SDK, runtime, and llama.cpp backend

  4. 04
    Planned

    Proton LPU-E0 RTL and verification

  5. 05
    Future

    FPGA reference system

  6. 06
    Future

    Open ASIC exploration

  7. 07
    Future

    Proton LPU-E1 multi-tile edge architecture

  8. 08
    Long-term

    Proton LPU-S1 server research

11

FOUNDER / CEREBRAL CHIPS

Meet the architect connecting modern AI to edge machines.

Cerebral Chips is building a cross-layer engineering team around physical AI, accelerator architecture, compiler and runtime systems, quantized compute, and open hardware–software enablement.

Pratik Kedar standing beside a waterfall
FOUNDER / 01CEREBRAL CHIPS

PLEASE MEET

Pratik R. Kedar

Physical AI Architect and Hardware–Software Ecosystem Enabler

Leading the path from AI workloads to accelerator architecture.

LinkedInPublications

Pratik R. Kedar is a Physical AI architect and engineering leader building the hardware–software ecosystem required for modern AI acceleration. His work connects model compilers, MLIR and IREE, runtimes, optimized DSP and NPU kernels, RISC-V vector and matrix execution, SoC enablement, and the architectural decisions that shape efficient edge systems. Across GlobalFoundries, Texas Instruments, and Cadence, he has led and enabled cross-layer efforts that turn accelerator capabilities into usable AI platforms. At Cerebral Chips, he brings that full-stack perspective to workload-driven architecture, memory systems, quantized compute, firmware, RTL, verification, and open engineering.

INDUSTRY EXPERIENCE

Physical AI Architecture and Enablement

Architecting and enabling physical AI across MIPS and ARC compute, IREE and MLIR integration, multi-core inference, and vector or matrix acceleration.

Edge AI Platform Enablement

Enabled TIDL compiler and C7x/MMA acceleration for automotive and industrial Jacinto SoCs, connecting models to heterogeneous edge hardware.

AI Accelerator Software and Enablement

Advanced compiler and neural-network library enablement for Tensilica Vision DSP platforms and edge inference workloads.

BUILD / RESEARCH / VERIFY

Help build the compute foundation for intelligent machines.

Cerebral Chips is opening the work carefully—one validated artifact, reference platform, and architecture decision at a time.

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