Build the whole system around the work AI actually performs.
Cerebral Chips is building a cross-functional hardware–software effort for local language intelligence—from workload evidence and developer tools to accelerator architecture and verification.
Early-stage architecture, prototype, and open-source research phase
Every machine should be able to think where it operates.
Useful intelligence should not always depend on a permanent round trip to the cloud. Local execution can give product teams stronger control over responsiveness, privacy boundaries, connectivity, and the economics of repeated inference.
That requires more than adding a matrix engine to a device. The model format, numerical behavior, runtime, compiler path, memory system, firmware, compute architecture, and validation process have to be designed as one measurable system.
Local AI is a system problem.
The workload is the starting point.
Prefill and decode stress a machine differently. Tensor shapes, quantization, operator mix, and memory traffic belong in the architecture conversation from the beginning.
Hardware and software share one contract.
An accelerator becomes useful only when models, runtimes, kernels, firmware, memory movement, and developer feedback can reach it coherently.
Evidence should constrain ambition.
Simulation, reference comparison, verification, and review determine what advances. Status labels keep research direction separate from completed capability.
Cross-layer experience for a cross-layer machine.
Cerebral Chips is being shaped as a hardware–software team. Its founding technical direction brings together AI workloads, compilers, runtimes, kernels, RISC-V execution, SoC enablement, and accelerator architecture.
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Pratik R. Kedar
Physical AI Architect and Hardware–Software Ecosystem Enabler
Leading the path from AI workloads to accelerator architecture.
Pratik R. Kedar is a Physical AI architect and engineering leader building the hardware–software ecosystem required for modern AI acceleration. His work connects model compilers, MLIR and IREE, runtimes, optimized DSP and NPU kernels, RISC-V vector and matrix execution, SoC enablement, and the architectural decisions that shape efficient edge systems. Across GlobalFoundries, Texas Instruments, and Cadence, he has led and enabled cross-layer efforts that turn accelerator capabilities into usable AI platforms. At Cerebral Chips, he brings that full-stack perspective to workload-driven architecture, memory systems, quantized compute, firmware, RTL, verification, and open engineering.
Physical AI Architecture and Enablement
Architecting and enabling physical AI across MIPS and ARC compute, IREE and MLIR integration, multi-core inference, and vector or matrix acceleration.
Edge AI Platform Enablement
Enabled TIDL compiler and C7x/MMA acceleration for automotive and industrial Jacinto SoCs, connecting models to heterogeneous edge hardware.
AI Accelerator Software and Enablement
Advanced compiler and neural-network library enablement for Tensilica Vision DSP platforms and edge inference workloads.How the team intends to build.
Measure before freezing
Use workload evidence and analytical models to narrow the architecture before hardening implementation choices.
Make boundaries explicit
Separate proposed specifications, prototypes, verified artifacts, and longer-term direction in both engineering and communication.
Design across layers
Treat model behavior, numerical formats, software interfaces, memory movement, and compute as connected decisions.
Automate with independent checks
Use agents to accelerate iteration while compilation, reference models, randomized tests, coverage, and human review gate acceptance.
Open where the work is ready to be inspected and maintained.
The intended publication path includes architecture notes, workload models, software, RTL, and verification evidence where ownership, licensing, documentation, and validation status are clear.
- No unpublished repository placeholders
- No benchmark without method and limitations
- No generated artifact accepted on confidence alone
- No roadmap direction presented as shipped capability
Bring the workload, constraint, or architecture question.
Focused technical exchanges are the best place to begin.